Flat panel liquid crystal display (LCD) arrays may be formed using a photolithographic method, where a repeated reticle image is used for patterning a large portion of the entire array. The reticle may be mounted on a precision step-and-repeat stage in a projection exposure system to incrementally expose portions of a photoresist layer on a substrate to the reticle pattern until the entire intended array area has been exposed. In this way, a single reticle can be used to create a very large pattern containing a repeated reticle pattern.
It has been found difficult to precisely match up the edge of a previously exposed reticle pattern on a substrate with the edge of the stepped reticle image adjacent to the previously exposed reticle pattern. Precise alignment of reticle patterns is not critical if flat panel transistors are not formed at the boundary between adjacent reticle patterns.
However, precise alignment and some degree of overlap of adjacent patterns are required to properly form transistors along the boundary of adjacent reticle patterns. Consequently, for these types of flat panel arrays there is some imperfect overlap between adjacent reticle patterns which may be visually perceived upon a close inspection of the resulting flat panel display. The imperfectly overlapping patterns are perceived in the final display because this imperfect overlap distorts the resulting transistor pattern and increases the exposure time of the photoresist layer over the substrate when forming the array. The exposure time of a photoresist layer to masked radiation affects the line widths of the features formed in the photoresist. Whether these line widths are reduced or enlarged depends upon whether the photoresist is a positive or negative photoresist and on the particular processing used to fabricate the array.
In a high quality thin film transistor (TFT) LCD array, the manufacturer typically does not want more than a 0.1-0.2 micron feature change in the portion of the array where the reticle patterns overlap, since a greater change in feature size will significantly affect the brightness (i.e., transistor gain) of a pixel located in that portion of the array. In a typical process for forming a TFT LCD array, an overlap between adjacent reticle patterns is about 1 mm. Each pixel is approximately 0.2 mm, so that the overlap affects five pixels. Hence, if this overlapped portion is not a precise overlap or is too overexposed due to the double exposures from adjacent reticle images, the abrupt increased brightness of five adjacent pixels around each reticle pattern may be perceived by the user.
What is needed is an improved process for stitching together repeated reticle patterns formed in a photoresist layer on a substrate so as to precisely blend the borders of the repeated reticle patterns.